1. Field of the Invention
The present invention relates to a semiconductor-memory device, and particularly to output timing of a data signal of synchronous semiconductor memory device.
2. Description of the Background Art
In accordance with remarkable increase in operation speed of CPUs (Central Processing Units), it has been strongly required to increase operation speeds of main storage devices. Therefore, SDRAMs (Synchronous Dynamic Random Access Memories), which can perform fast data input/output operations in synchronization with an external clock signal, have been developed and used.
In general, the SDRAM internally includes a clock generating circuit, which generates an internal clock signal synchronized with an external clock signal, and internal circuits of the SDRAM are controlled based on the internal clock signal. The clock generating circuit is formed of a DLL (Delay Locked Loop) circuit or the like, and generates the internal clock signal delayed by a predetermined amount with respect to the external clock signal.
In the operation of externally transmitting data signals to or from the SDRAM, therefore, the internal clock signal having the predetermined delay amount is used for controlling data output timing of an output buffer, which controls output of the data signals.
In the SDRAM having a high operation frequency for achieving fast data transfer, an output buffer driving an output load, which is formed of downstream circuits or the like receiving the data signal, is configured to have a large current drive power. Such a current drive power is set by increasing transistor sizes of transistors forming the output buffer.
However, if the operation frequency is low, the large current drive power of the output buffer causes excessive charging/discharging of the output load. This results in rapid change in voltage, and causes overshoot or undershoot. In this case, therefore, the transistor sizes of transistors in the output buffer are reduced to suppress the current drive power, as disclosed, e.g., in Japanese Patent Laying-Open Nos. 10-308096 and 2003-085974.
Although the current drive power of the output buffer is adjusted in accordance with the operation frequency as described above, the internal clock determining the data output timing is always controlled to have a constant delay amount by the clock generating circuit.
Therefore, if the current drive power of the output buffer is large with respect to a constant output load, a voltage on an output node changes rapidly, and the data output timing can be accurately synchronized with the internal clock signal. Meanwhile, if the current drive power of the output buffer is small, the voltage on the output node changes slowly, and the data output timing is shifted from the internal clock signal.
A time from activation of the external clock signal to output of data from a main storage device is referred to as an operation delay time (access time) of a memory core arranged in a microprocessor or the like, and is usually defined in a data sheet as a specification item representing an operation speed. Therefore, if the access time changes due to adjustment of the drive power of the output buffer, this impairs the reliability of products.